Multithreaded hardware computer architecture may have an Interval Timer Counter (ITC) shared by two or more hardware threads on a same processor core, for example, a CPU (central processing unit) core. The ITC advances irrespective of which hardware thread is executing on the processor core. An operating system (OS) for the processor core has no control over context switch events of the hardware threads. For example, an operation available to the hardware threads comprises a simple yield instruction such as hint@pause or PAL_HALT_LIGHT. Measurements are not performed on a per-hardware thread basis. An inability to accurately measure core execution time and core utilization from algorithms based on the ITC result in a double counting of execution time and a doubling of core utilization metrics, for example, for two hardware threads.